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This lesson examines two foundational computer architectures — the Von Neumann model and the Harvard model — that underpin every modern processor. At A-Level you are expected to compare them in depth, explain why each is suited to particular use-cases, and discuss variants such as the Modified Harvard Architecture used in most desktop CPUs today.
The Von Neumann architecture was proposed by the mathematician John von Neumann in 1945. Its defining characteristic is the stored-program concept: both the program instructions and the data they operate on are held in the same memory and accessed via a single shared bus.
| Component | Role |
|---|---|
| Processor (CPU) | Fetches, decodes and executes instructions |
| Main memory (RAM) | Stores both program instructions and data in the same address space |
| System bus | A single set of buses (address bus, data bus, control bus) connecting CPU and memory |
| Input / Output | Peripheral devices connected through I/O controllers |
Because there is only one bus between the CPU and memory, the processor cannot fetch an instruction and read/write data at the same time. The bus becomes a bottleneck — the processor may be idle waiting for data, even though it could otherwise be doing useful work.
Exam Tip: The Von Neumann bottleneck is a favourite topic in A-Level exams. Be precise: the bottleneck arises because instructions and data share a single bus, not just because they share the same memory. State both facts for full marks.
The Harvard architecture uses physically separate memories and buses for instructions and data. It was originally developed at Harvard University for the Mark I relay computer.
| Component | Role |
|---|---|
| Processor (CPU) | Fetches, decodes and executes instructions |
| Instruction memory | Stores program instructions only |
| Data memory | Stores data only |
| Instruction bus | Dedicated bus connecting CPU to instruction memory |
| Data bus | Dedicated bus connecting CPU to data memory |
Most modern desktop and laptop processors use a Modified Harvard architecture. This is essentially a Von Neumann design at the main-memory level (programs and data share RAM) but with separate Level 1 (L1) caches inside the CPU — one for instructions and one for data.
CPU
┌──────────────────┐
│ ┌─────┐ ┌─────┐ │
│ │ L1-I │ │ L1-D │ │ ← Separate instruction and data caches (Harvard-style)
│ └──┬──┘ └──┬──┘ │
│ └───┬───┘ │
│ L2 Cache │
└────────┬─────────┘
│
Unified Main Memory ← Single shared memory (Von Neumann-style)
This hybrid gets the speed advantage of Harvard (simultaneous instruction and data access at the cache level) and the flexibility of Von Neumann (a single main memory for both programs and data).
| Feature | Von Neumann | Harvard | Modified Harvard |
|---|---|---|---|
| Memory for instructions and data | Shared | Separate | Shared main memory, split caches |
| Buses | Single shared bus | Separate instruction and data buses | Shared main bus, split at cache level |
| Von Neumann bottleneck | Yes | No | Reduced (mitigated by caches) |
| Cost / complexity | Lower | Higher | Moderate |
| Typical use | General-purpose PCs (historically) | DSPs, microcontrollers, embedded systems | Modern desktop/laptop CPUs |
| Self-modifying code | Possible | Not directly possible | Possible (via main memory) |
Exam Tip: When asked to "state an application of the Harvard architecture", always give a concrete example (e.g. "digital signal processors used in audio processing" or "PIC microcontrollers used in embedded systems"). Vague answers such as "in small devices" will not score full marks.